View ADE7752_297582.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Polyphase Energy Metering IC with Pulse Output ADE7752
FEATURES
High accuracy, supports 50 Hz/60 Hz IEC 687/61036 Less than 0.1% error over a dynamic range of 500 to 1 Compatible with 3-phase/3-wire delta and 3-phase/4-wire Wye configurations The ADE7752* supplies average real power on the frequency outputs F1 and F2 High frequency output CF is intended for calibration and supplies instantaneous real power Logic output NEGP indicates a potential miswiring or negative power for each phase Direct drive for electromechanical counters and 2-phase stepper motors (F1 and F2) Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time On-chip power supply monitoring On-chip creep protection (no load threshold) On-chip reference 2.4 V 8% (20 ppm/C typical) with external overdrive capability Single 5 V supply, low power (60 mW typical) Low cost CMOS process
*Patent pending.
GENERAL DESCRIPTION
The ADE7752 is a high accuracy polyphase electrical energy measurement IC. The part specifications surpass the accuracy requirements as quoted in the IEC61036 standard. The only analog circuitry used in the ADE7752 is in the ADCs and reference circuit. All other signal processing (e.g., multiplication, filtering, and summation) is carried out in the digital domain. This approach provides superior stability and accuracy over extremes in environmental conditions and over time. The ADE7752 supplies average real power information on the low frequency outputs, F1 and F2. These logic outputs may be used to directly drive an electromechanical counter or to interface with an MCU. The CF logic output gives instantaneous real power information. This output is intended to be used for calibration purposes. The ADE7752 includes a power supply monitoring circuit on the VDD pin. The ADE7752 will remain inactive until the supply voltage on VDD reaches 4 V. If the supply falls below 4 V, the ADE7752 will also be reset and no pulses will be issued on F1, F2, and CF. Internal phase matching circuitry ensures that the voltage and current channels are phase matched. An internal no load threshold ensures the part does not exhibit any creep when there is no load. The ADE7752 is available in a 24-lead SOIC package.
FUNCTIONAL BLOCK DIAGRAM
ABS
17
VDD 3
IAP 5 IAN 6 VAP 16
ADC ADC
HPF
X LPF
PHASE CORRECTION
POWER SUPPLY MONITOR
ADE7752
X LPF
IBP IBN
7 8
ADC HPF ADC
2
DGND
VBP 15
PHASE CORRECTION
19 CLKIN 20 CLKOUT
ICP
9
ICN 10 VCP 14 VN 13 2.4V REF
11
ADC ADC 4k
12
HPF
PHASE CORRECTION
4
LPF
X
DIGITAL-TO-FREQUENCY CONVERTER
02676-A-001
18
21
22
23
24
1
AGND
REFIN/OUT
NEGP
SCF
S0
S1
F2
F1
CF
Figure 1. Functional Block Diagram Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADE7752 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Characteristics..................................................................... 4 Absolute Maximum Ratings............................................................ 5 Terminology ...................................................................................... 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 9 Test Circuit ...................................................................................... 11 Theory of Operation ...................................................................... 12 Power Factor Considerations.................................................... 12 Nonsinusoidal Voltage and Current......................................... 13 Analog Inputs.................................................................................. 14 Current Channels ....................................................................... 14 Voltage Channels ........................................................................ 14 Typical Connection Diagrams ...................................................... 15 Current Channel Connection................................................... 15 Voltage Channels Connection .................................................. 15 Meter Connections..................................................................... 15 Power Supply Monitor ................................................................... 17 HPF and Offset Effects .............................................................. 17 Digital-to-Frequency Conversion ................................................ 18 Mode Selection of the Sum of the Three Active Energies .... 19 Power Measurement Considerations....................................... 19 Transfer Function ........................................................................... 20 Frequency Outputs F1 and F2 .................................................. 20 Frequency Output CF ................................................................ 21 Selecting a Frequency for an Energy Meter Application........... 22 Frequency Outputs..................................................................... 22 No Load Threshold .................................................................... 23 Negative Power Information..................................................... 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24
REVISION HISTORY
Location 9/03--Data Sheet Changed from Rev. A to Rev. B Updated Format................................................................................................................................................................................................... Universal Change to Figure 19 .........................................................................................................................................................................................................15 5/03--Data Sheet Changed from Rev. 0 to Rev. A Changed F1-5 to F1-7 ............................................................................................................................................................................................. Universal Change to Figure 6 ...........................................................................................................................................................................................................10 Changes to Frequency Outputs F1 and F2 section ......................................................................................................................................................13 Replaced Table II ..............................................................................................................................................................................................................13 Changes to Examples 1, 2, and 3.....................................................................................................................................................................................14 Replaced Table III .............................................................................................................................................................................................................14 Replaced Tables IV, V, and VI ..........................................................................................................................................................................................15 Changes to SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION section.......................................................................15 Changes to NO LOAD THRESHOLD section.............................................................................................................................................................16 Replaced Table VII............................................................................................................................................................................................................16 Page
Rev. B | Page 2 of 24
ADE7752 SPECIFICATIONS
Table 1. VDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz, TMIN to TMAX = -40C to+ 85C
Parameter ACCURACY1, 2 Measurement Error on Current Channel Phase Error between Channels PF = 0.8 Capacitive PF = 0.5 Capacitive AC Power Supply Rejection Output Frequency Variation (CF) DC Power Supply Rejection Output Frequency Variation (CF) ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) Bandwidth (-3 dB) ADC Offset Error1, 2 Gain Error REFERENCE INPUT REFIN/OUT Input Voltage Range Input Impedance Input Capacitance ON-CHIP REFERENCE Reference Error Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS3 ACF, S0, S1, and ABS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS3 F1 and F2 Output High Voltage, VOH Output Low Voltage, VOL CF and NEGP Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY VDD IDD Conditions Voltage Channel with Full-Scale Signal (500 mV), 25C, Over a Dynamic Range of 500 to 1 Min Typ Max Unit
0.1 0.1 0.1
% Reading (Degrees) (Degrees)
SCF = 0; S0 = S1 = 1 IA = IB = IC = 100 mV rms, VA = VB = VC = 100 mV rms, @ 50 Hz, Ripple on VDD of 200 mV rms @ 100 Hz S1 = 1; S0 = SCF = 0 V1 = 100 mV rms, V2 = 100 mV rms, VDD = 5 V 250 mV See Analog Inputs Section VAP-VN, VBP-VN, VCP-VN, IAP-IAN, IBP-IBN, ICP-ICN CLKIN = 10 MHz CLKIN/256, CLKIN = 10 MHz External 2.5 V Reference, IA = IB = IC = 500 mV dc 2.4 V + 8% 2.4 V - 8%
0.01 0.1 0.5 370 410 14 25 9 2.6 2.2 3.3 10
% Reading % Reading V peak Diff. k kHz mV % Ideal V V k pF mV ppm/C MHz
Nominal 2.4 V 200 25 All Specifications for CLKIN of 10 MHz 10
VDD = 5 V 5% VDD = 5 V 5% Typically 10 nA, VIN = 0 V to VDD
2.4 0.8 3 10
V V A pF
ISOURCE = 10 mA, VDD = 5 V ISINK = 10 mA, VDD = 5 V VDD = 5 V, ISOURCE = 5 mA VDD = 5 V, ISINK = 5 mA For Specified Performance 5 V 5%
4.5 0.5 4 0.5 4.75 12 5.25 16
V V V V V mA
1 2
See Terminology section for explanation of specifications. See plots in Typical Performance Characteristics. 3 Sample tested during initial release and after any redesign or process change that may affect this parameter.
Rev. B | Page 3 of 24
ADE7752 TIMING CHARACTERISTICS
Table 2. VDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz, TMIN to TMAX = -40C to +85C 1, 2
Parameter t1 3 t2 t3 t43, 4 t55 t6 275 See Table 6 1/2 t2 96 See Table 7 CLKIN/4 Conditions F1 and F2 Pulse Width (Logic High) Output Pulse Period. See Transfer Function section. Time between F1 Falling Edge and F2 Falling Edge CF Pulse Width (Logic High) CF Pulse Period. See Transfer Function section. Minimum Time between F1 and F2 Pulse Unit ms sec sec ms sec sec
1 2
Sample tested during initial release and after any redesign or process change that may affect this parameter. See Figure 2. 3 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See Frequency Outputs section. 4 CF is not synchronous to F1 or F2 frequency outputs. 5 The CF pulse is always 1 s in the high frequency mode. See Frequency Outputs section.
t1
F1
t6 t2
F2
t3 t4 t5
CF
Figure 2. Timing Diagram for Frequency Outputs
Rev. B | Page 4 of 24
02676-A-003
ADE7752 ABSOLUTE MAXIMUM RATINGS
Table 3. TA = 25C, unless otherwise noted
Parameter VDD to AGND VDD to DGND Analog Input Voltage to AGND VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN, ICP, and ICN Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature 24-Lead SOIC, Power Dissipation JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +7 V -0.3 V to +7 V
-6 V to +6 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +85C -65C to +150C 150C 88 mW 250C/W 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 5 of 24
ADE7752 TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the ADE7752 is defined by the following formula:
Energy Registered by ADE7752-True Energy Percentage Error = x 100% True Energy
same input signal levels. Any error introduced is expressed as a percentage of reading. See definition for Measurement Error. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. The supply is then varied 5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of reading.
Error between Channels
The HPF (high-pass filter) in the current channel has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is also placed in the current channel. The phase correction network ensures a phase match between the current channels and voltage channels to within 0.1 over a range of 45 Hz to 65 Hz and 0.2 over a range of 40 Hz to 1 kHz. See Figure 25 and Figure 26.
ADC Offset Error
This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see an analog input signal offset. However, as the HPF is always present, the offset is removed from the current channel and the power calculation is not affected by this offset.
Gain Error
The gain error of the ADE7752 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7752 transfer function. See the Transfer Function section.
Power Supply Rejection
This quantifies the ADE7752 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at a nominal supply (5 V) is taken. A 200 mV rms/100 Hz signal is then introduced onto the supply and a second reading is obtained under the
Rev. B | Page 6 of 24
ADE7752 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CF 1 DGND 2 VDD 3 NEGP 4 IAP 5 IAN 6
24 23 22 21
F1 F2 S1 S0 CLKOUT
CLKIN TOP VIEW IBP 7 (Not to Scale) 18 SCF
19 17 16 15 14 13
ADE7752
20
IBN 8 ICP 9 ICN 10 AGND 11 REFIN/OUT 12
ABS VAP
02676-A-003
VBP VCP VN
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 Mnemonic CF DGND Description Calibration Frequency Logic Output. The CF logic output gives instantaneous real power information. This output is intended to be used for calibration purposes. See the SCF pin description. This provides the ground reference for the digital circuitry in the ADE7752, i.e., multiplier, filters, and digital-tofrequency converter. Because the digital return currents in the ADE7752 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7752. The supply voltage should be maintained at 5 V 5% for specified operation. This pin should be decoupled to DGND with a 10 F capacitor in parallel with a 100 nF ceramic capacitor. This logic output will go logic high when negative power is detected on any of the three phase inputs, i.e., when the phase angle between the voltage and the current signals is greater than 90. This output is not latched and will be reset when positive power is once again detected. See the Negative Power Information section. Analog Inputs for Current Channel. This channel is intended for use with the current transducer and is referenced in this document as the current channel. These inputs are fully differential voltage inputs with maximum differential input signal levels of 0.5 V. See the Analog Inputs section. Both inputs have internal ESD protection circuitry; in addition, an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. This pin provides the ground reference for the analog circuitry in the ADE7752, i.e., ADCs, temperature sensor, and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, and so on. To keep ground noise around the ADE7752 to a minimum, the quiet ground plane should only connect to the digital ground plane at one point. It is acceptable to place the entire device on the analog ground plane. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V 8% and a typical temperature coefficient of 20 ppm/C. An external reference source may also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 F ceramic capacitor. Analog Inputs for the Voltage Channel. This channel is intended for use with the voltage transducer and is referenced in this document as the voltage channel. These inputs are single-ended voltage inputs with a maximum signal level of 0.5 V with respect to VN for specified operation. All inputs have internal ESD protection circuitry; in addition, an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. This logic input is used to select the way the three active energies from the three phases are summed. This offers the designer the capability to do the arithmetical sum of the three energies (ABS logic high) or the sum of the absolute values (ABS logic low). See the Mode Selection of the Sum of the Three Active Energies section. Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. Table 7 shows how the calibration frequencies are selected. Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7752. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer's data sheet for load capacitance requirements.
Rev. B | Page 7 of 24
3
VDD
4
NEGP
5, 6; 7, 8; 9, 10
IAP, IAN; IBP, IBN; ICP, ICN
11
AGND
12
REFIN/OUT
13-16
VN, VCP, VBP, VAP
17
ABS
18 19
SCF CLKIN
ADE7752
Pin No. 20 Mnemonic CLKOUT Description A crystal can be connected across this pin and CLKIN as described previously to provide a clock source for the ADE7752. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or when a crystal is being used. These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion. This offers the designer greater flexibility when designing the energy meter. See the Selecting a Frequency for an Energy Meter Application section. Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can be used to drive electromechanical counters and 2-phase stepper motors directly. See the Transfer Function section.
21, 22
S0, S1
24, 23
F1, F2
Rev. B | Page 8 of 24
ADE7752 TYPICAL PERFORMANCE CHARACTERISTICS
1
0.5 0.4 0.3
WYE CONNECTION ON-CHIP REFERENCE PHASE C
PHASE A
1.0 0.8 0.6
WYE CONNECTION ON-CHIP REFERENCE +85C PF = 1
ERROR (% of Reading)
0.1 0 -0.1 -0.2 -0.3
02676-A-004
ERROR (% of Reading)
0.2
PHASE A + B + C
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0.1 10 1 CURRENT CHANNEL (% of Full Scale)
02676-A-007
PHASE B
+25C PF = 1
-40C PF = 1
-0.4 -0.5 0.1 10 1 CURRENT CHANNEL (% of Full Scale) 100
100
Figure 4. Error as a Percent of Reading with Internal Reference (Wye Connection)
1.0 0.8 0.6
ERROR (% of Reading)
Figure 7. Error as a Percent of Reading over Temperature with Internal Reference (Wye Connection)
0.5 0.4 0.3 DELTA CONNECTION ON-CHIP REFERENCE
WYE CONNECTION ON-CHIP REFERENCE +85C PF = +0.5 +25C PF = -0.5
PF = -0.5 PF = +1
0.2 0 -0.2 -0.4 -0.6
02676-A-005
ERROR (% of Reading)
0.4
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 1 10 CURRENT CHANNEL (% of Full Scale) 100
02676-A-008
+25C PF = +1 -40C PF = +0.5
PF = +0.5
-0.8 -1.0 0.1 1 10 100
CURRENT CHANNEL (% of Full Scale)
Figure 5. Error as a Percent of Reading over Power Factor with Internal Reference (Wye Connection)
0.5 0.4 0.3 WYE CONNECTION EXTERNAL REFERENCE +85C PF = +0.5
Figure 8. Error as a Percent of Reading over Power Factor with Internal Reference (Delta Connection)
0.5 WYE CONNECTION 0.4 EXTERNAL REFERENCE 0.3 ERROR (% of Reading) 0.2 0.1 0 -0.1 -0.2 -0.3
02676-A-006
ERROR (% of Reading)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 1 10
+85C PF = 1
+25C PF = +1
+25C PF = 1
-40C PF = +0.5
+25C PF = -0.5
-40C PF = 1
-0.4 -0.5 0.1 1 10 CURRENT CHANNEL (% of Full Scale)
100
100
CURRENT CHANNEL (% of Full Scale)
Figure 6. Error as a Percent of Reading over Power Factor with External Reference (Wye Connection)
Figure 9. Error as a Percent of Reading over Temperature with External Reference (Wye Connection)
Rev. B | Page 9 of 24
02676-A-009
ADE7752
0.5 0.4 0.3 WYE CONNECTION ON-CHIP REFERENCE
18
ERROR (% of Reading)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 45 50
PF = 1
15
N: 88 MEAN: 4.48045 SD: 3.23101 MIN: -2.47468 MAX: 12.9385 RANGE: 15.4132
12
PF = 0.5
9
6
02676-A-010
55 FREQUENCY (Hz)
60
65
0 -20
-15
-10
-5
0
5
10
15
20
CH_I PhA OFFSET (mV)
Figure 10. Error as a Percent of Reading over Frequency with an Internal Reference (Wye Connection)
0.5 0.4 0.3
ERROR (% of Reading)
Figure 12. Channel 1 Offset Distribution
0.5
WYE CONNECTION EXTERNAL REFERENCE
4.75V
0.4 0.3
WYE CONNECTION ON-CHIP REFERENCE
4.75V
0.2 0.1 0 -0.1 -0.2 -0.3
ERROR (% of Reading)
5V
0.2 0.1 0 -0.1 -0.2 -0.3
5V
5.25V
5.25V
02676-A-012
3
02676-A-011
-0.4 -0.5 0.1 10 1 CURRENT CHANNEL (% of Full Scale) 100
-0.4 -0.5 0.1 1 10
100
CURRENT CHANNEL (% of Full Scale)
Figure 11. Error as a Percent of Reading over Power Supply with External Reference (Wye Connection)
Figure 13. Error as a Percent of Reading over Power Supply with Internal Reference (Wye Connection)
Rev. B | Page 10 of 24
02676-A-013
ADE7752 TEST CIRCUIT
VDD 10F I
LOAD
100nF
3 17
1k RB 33nF 1k 33nF SAME AS IAP, IAN SAME AS IAP, IAN 1M 220V 1k 33nF SAME AS VAP SAME AS VAP
VDD 5 IAP
ABS F1 24 F2
23
K7 TO FREQ. COUNTER 22pF K8
ADE7752
6
IAN IBP IBN ICP ICN VAP VBP VCP
CF 1 CLKOUT 20
825
7 8 9 10 16 15 14
10MHz CLKIN 19 22pF S0 21 S1 22 SCF 18 REFIN/OUT 12 100nF 10F 1k
PS2501-1
VDD
NEGP 4 NOT CONNECTED VN AGND DGND
13 11 2
02676-A-014
1k 33nF
Figure 14. Test Circuit for Performance Curves
Rev. B | Page 11 of 24
ADE7752 THEORY OF OPERATION
The six voltage signals from the current and voltage transducers are digitized with ADCs. These ADCs are 16-bit second order - with an oversampling rate of 833 kHz. This analog input structure greatly simplifies transducer interface by providing a wide dynamic range for direct connection to the transducer and also simplifying the antialiasing filter design. A high-pass filter in the current channel removes the dc component from the current signal. This eliminates any inaccuracies in the real power calculation due to offsets in the voltage or current signals--see HPF and Offset Effects section. The real power calculation is derived from the instantaneous power signal. The instantaneous power signal is generated by a direct multiplication of the current and voltage signals of each phase. In order to extract the real power component (i.e., the dc component), the instantaneous power signal is low-pass filtered on each phase. Figure 15 illustrates the instantaneous real power signal and shows how the real power information can be extracted by low-pass filtering the instantaneous power signal. This method is used to extract the real power information on each phase of the polyphase system. The total real power information is then obtained by adding the individual phase real power. This scheme correctly calculates real power for nonsinusoidal current and voltage waveforms at all power factors. All signal processing is carried out in the digital domain for superior stability over temperature and time. The low frequency output of the ADE7752 is generated by accumulating the total real power information. This low frequency inherently means a long accumulation time between output pulses. The output frequency is therefore proportional to the average real power. This average real power information can, in turn, be accumulated (e.g., by a counter) to generate real energy information. Because of its high output frequency and therefore shorter integration time, the CF output is proportional to the instantaneous real power. This pulse is useful for system calibration purposes that would take place under steady load conditions.
POWER FACTOR CONSIDERATIONS
The method used to extract the real power information from the individual instantaneous power signal (i.e., by low-pass filtering) is still valid when the voltage and current signals of each phase are not in phase. Figure 16 displays the unity power factor condition and a DPF (displacement power factor) = 0.5, i.e., current signal lagging the voltage by 60, for one phase of the polyphase. If we assume the voltage and current waveforms are sinusoidal, the real power componen of the instantaneous power signal (i.e., the dc term) is given by:
V x 1 x cos(60) 2
VxI VxI 2 TIME
p(t) = i(t) x v(t) WHERE: v(t) = V x cos (t) i(t) = I x cos (t) p(t) = V x I {1+ cos (2t)} 2 INSTANTANEOUS POWER SIGNAL - p(t)
VxI 2
INSTANTANEOUS REAL POWER SIGNAL
VA x IA + VB x IB + VCxIC 2
HPF IAP IAN ADC MULTIPLIER VAP ADC HPF IBP IBN ADC MULTIPLIER VBP ADC HPF ICP ICN ADC MULTIPLIER VCP VN ADC LPF LPF
ABS INSTANTANEOUS TOTAL POWER SIGNAL
|X|
DIGITAL-TOFREQUENCY LPF |X| DIGITAL-TOFREQUENCY CF F1 F2
Figure 15. Signal Processing Block Diagram
Rev. B | Page 12 of 24
02676-A-015
|X|
ADE7752
This is the correct real power calculation.
INSTANTANEOUS POWER SIGNAL INSTANTANEOUS REAL POWER SIGNAL
i (t ) = I O + 2 x
n=0
V I x sin (nt )
n n
(2)
Vx I 2
0V CURRENT VOLTAGE INSTANTANEOUS POWER SIGNAL INSTANTANEOUS REAL POWER SIGNAL
where: i(t) is the instantaneous current IO is the dc component In is the rms value of current harmonic n n is the phase angle of the current harmonic Using Equations 1 and 2, the real power, P, can be expressed in terms of its fundamental real power (P1) and harmonic real power (PH). P = P1 + PH
Vx I x cos(60) 2 0V
02676-A-016
where:
P1 = V 1x I 1 cos 1 1 = 1 - 1
VOLTAGE
60
CURRENT
(3)
Figure 16. DC Component of Instantaneous Power Signal Conveys Real Power Information PF < 1
PH =
V
n =1
n
x I n cos n
(4)
NONSINUSOIDAL VOLTAGE AND CURRENT
The real power calculation method also holds true for nonsinusoidal current and voltage waveforms. All voltage and current waveforms in practical applications will have some harmonic content. Using the Fourier Transform, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content:
v (t ) = Vo + 2 x
n = n - n As can be seen from Equation 4, a harmonic real power component is generated for every harmonic, provided that harmonic is present in both the voltage and current waveforms. The power factor calculation has been shown to be accurate in the case of a pure sinusoid. Therefore, the harmonic real power must also correctly account for power factor since it is made up of a series of pure sinusoids. Note that the input bandwidth of the analog inputs is 14 kHz with a master clock frequency of 10 MHz.
n=0
V
n
x sin (nt + n )
(1)
where: v(t) is the instantaneous voltage VO is the average value Vn is the rms value of voltage harmonic n and n is the phase angle of the voltage harmonic
Rev. B | Page 13 of 24
ADE7752 ANALOG INPUTS
CURRENT CHANNELS
The voltage outputs from the current transducers are connected to the ADE7752 current channels, which are fully differential voltage inputs. IAP, IBP, and ICP are the positive inputs for IAN, IBN, and ICN, respectively. The maximum peak differential signal on the current channel should be less than 500 mV (353 mV rms for a pure sinusoidal signal) for the specified operation.
IAP-IAN +500mV IAP DIFFERENTIAL INPUT 500mV MAX PEAK VCM COMMON-MODE 25mV MAX -500mV VCM
02676-A-017
VOLTAGE CHANNELS
The output of the line voltage transducer is connected to the ADE7752 at this analog input. Voltage channels are a pseudodifferential voltage input. VAP, VBP, and VCP are the positive inputs with respect to VN. The maximum peak differential signal on the voltage channel is 500 mV (353 mV rms for a pure sinusoidal signal) for specified operation. Figure 18 illustrates the maximum signal levels that can be connected to the ADE7752's voltage channels.
VAP-VN +500mV VAP DIFFERENTIAL INPUT 500mV MAX PEAK VCM COMMON-MODE 25mV MAX -500mV VCM AGND
02676-A-018
IA
IAN
AGND
VA
VN
Figure 17. Maximum Signal Levels, Current Channel
Figure 17 illustrates the maximum signal levels on IAP and IAN. The maximum differential voltage between IAP and IAN is 500 mV. The differential voltage signal on the inputs must be referenced to a common mode, e.g., AGND. The maximum common-mode signal shown in Figure 17 is 25 mV.
Figure 18. Maximum Signal Levels, Voltage Channel
Voltage channels must be driven from a common-mode voltage, i.e., the differential voltage signal on the input must be referenced to a common mode (usually AGND). The analog inputs of the ADE7752 can be driven with common-mode voltages of up to 25 mV with respect to AGND. However, best results are achieved using a common mode equal to AGND.
Rev. B | Page 14 of 24
ADE7752 TYPICAL CONNECTION DIAGRAMS
CURRENT CHANNEL CONNECTION
Figure 19 shows a typical connection diagram for the current channel (IA). A CT (current transformer) is the current transducer selected for this example. Notice the common-mode voltage for the current channel is AGND and is derived by center tapping the burden resistor to AGND. This provides the complementary analog input signals for IAP and IAN. The CT turns ratio and burden resistor Rb are selected to give a peak differential voltage of 500 mV at maximum load.
CT Rb Rf Cf 500mV IAP IAN
METER CONNECTIONS
In 3-phase service, two main power distribution services exist: 3-phase 4-wire or 3-phase 3-wire. The additional wire in the 3-phase 4-wire arrangement is the neutral wire. The voltage lines have a phase difference of 120 (2/3 radians) between each other. See Equation 5.
V A (t ) = 2 x V A x cos ( l t ) 2 V B (t ) = 2 x V B x cos l t + 3 4 V C (t ) = 2 x VC x cos l t + 3
02676-A-019
(5)
IP PHASE NEUTRAL
Rf
Cf
where VA, VB, and VC represent the voltage rms values of the different phases. The current inputs are represented by Equation 6: I A (t ) = 2 I A x cos ( l t + A ) 2 I B (t ) = 2 I B x cos l t + + B 3 4 I C (t ) = 2 I C x cos l t + + C 3 (6)
Figure 19. Typical Connection for Current Channels
VOLTAGE CHANNELS CONNECTION
Figure 20 shows two typical connections for the voltage channel. The first option uses a PT (potential transformer) to provide complete isolation from the main voltage. In the second option, the ADE7752 is biased around the neutral wire, and a resistor divider is used to provide a voltage signal proportional to the line voltage. Adjusting the ratio of Ra, Rb, and VR is also a convenient way of carrying out a gain calibration on the meter.
Rf Cf 500mV Rf AGND PHASE NEUTRAL Ra* Rb* VR* Cf Cf VAP VN
where IA, IB, and IC represent the rms value of the current of each phase and A, B, and C represent the phase difference of the current and voltage channel of each phase. The instantaneous powers can then be calculated as follows:
PT
PA(t) = VA(t) x IA(t) PB(t) = VB(t) x IB(t) PC(t) = VC(t) x IC(t) Then:
PA (t ) = VA x I A x cos( A ) - VA x I A x cos (2lt + A ) 4 (7) PB (t ) = VB x I B x cos(B ) - VB x I B x cos 2lt + + B 3 8 + C PC (t ) = VC x IC x cos(C ) - VC x IC x cos 2lt + 3
500mV Rf
VAP VN Cf
02676-A-018
PHASE NEUTRAL
* Ra >> Rf + VR; * Rb + VR = Rf
Figure 20. Typical Connections for Voltage Channels
As shown in Equation 7, in the ADE7752, the real power calculation per phase is made when current and voltage inputs of one phase are connected to the same channel (A, B, or C). Then the summation of each individual real power calculation gives the total real power information, P(t) = PA(t) + PB(t) + PC(t).
Rev. B | Page 15 of 24
ADE7752
Figure 21 shows the connections of the ADE7752's analog inputs with the power lines in a 3-phase 3-wire Delta service.
Ra* Rb* VR* Rb* CT PHASE A PHASE C SOURCE Rf PHASE B CT Cf VN LOAD VAP IAP IAN ANTIALIASING FILTERS Cf
Figure 22 shows the connections of the ADE7752's analog inputs with the power lines in a 3-phase 4-wire Wye service.
Ra* Rb* VR* Rb* CT VAP IAP IAN ANTIALIASING FILTERS CT PHASE A SOURCE PHASE B Ra* Rb* PHASE C VR* CT Cf Rb* ANTIALIASING FILTERS IBP IBN VBP Cf
Ra* Rb* VR*
Cf
Rb*
ANTIALIASING FILTERS IBP IBN VBP
02676-A-021
Ra* Rb* VR* Rf
Cf
Rb*
ANTIALIASING FILTERS ICP ICN VCP LOAD
* Ra >> Rf + VR; * Rb + VR = Rf
Figure 21. 3-Phase 3-Wire Meter Connection with ADE7752
CF
* Ra >> Rf + VR; * Rb + VR = Rf
Note that only two current inputs and two voltage inputs of the ADE7752 are used in this case. The real power calculated by the ADE7752 does not depend on the selected channels.
Figure 22. 3-Phase 4-Wire Meter Connection with ADE7752
Rev. B | Page 16 of 24
02676-A-022
VN
ADE7752 POWER SUPPLY MONITOR
The ADE7752 contains an on-chip power supply monitor. The power supply (VDD) is continuously monitored by the ADE7752. If the supply is less than 4 V 5%, the outputs of the ADE7752 will be inactive. This is useful to ensure correct device startup at power-up and power-down. The power supply monitor has built-in hysteresis and filtering. This gives a high degree of immunity to false triggering due to noisy supplies. As can be seen from Figure 23, the trigger level is nominally set at 4 V. The tolerance on this trigger level is about 5%. The power supply and decoupling for the part should be such that the ripple at VDD does not exceed 5 V 5% as specified for normal operation.
VDD 5V 4V
VOS x IOS Vx I 2 DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULATION
IOS x V
02676-A-024
VOS x I 0 2 FREQUENCY - RAD/S
Figure 24. Effect of Channel Offset on the Real Power Calculation
The HPF in the current channels have an associated phase response that is compensated for on-chip. Figure 25 and Figure 26 show the phase error between channels with the compensation network. The ADE7752 is phase compensated up to 1 kHz as shown. This ensures correct active harmonic power calculation even at low power factors.
TIME 0.07 0.06
0V
02676-A-023
INTERNAL RESET INACTIVE
ACTIVE
INACTIVE
0.05
PHASE (Degrees)
0.04 0.03 0.02 0.01 0 -0.01
02676-A-025
Figure 23. On-Chip Power Supply Monitor
HPF AND OFFSET EFFECTS
Figure 24 shows the effect of offsets on the real power calculation. As can be seen, an offset on the current channel and voltage channel contribute a dc component after multiplication. Since this dc component is extracted by the LPF and is used to generate the real power information for each phase, the offsets will have contributed a constant error to the total real power calculation. This problem is easily avoided by the HPF in the current channels. By removing the offset from at least one channel, no error component can be generated at dc by the multiplication. Error terms at cos(t) are removed by the LPF and the digital-to-frequency conversion. See the Digital-toFrequency Conversion section.
0
100
200
300
400 500 600 700 FREQUENCY (Hz)
800
900 1000
Figure 25. Phase Error between Channels (0 Hz to 1 kHz)
0.010 0.008 0.006
PHASE (Degrees)
0.004 0.002 0 -0.002 -0.004
{V cos(t ) + VOS }x {I cos(t ) + I OS } =
+ VOS x I OS + VOS x I cos(t ) + I OS x V cos(t ) 2 V xI + x cos(2t ) 2 V xI
40
45
50
55 60 FREQUENCY (Hz)
65
70
Figure 26. Phase Error between Channels (40 Hz to 70 Hz)
Rev. B | Page 17 of 24
02676-A-026
ADE7752 DIGITAL-TO-FREQUENCY CONVERSION
As previously described, after multiplication the digital output of the low-pass filter contains the real power information of each phase. However since this LPF is not an ideal "brick wall" filter implementation, the output signal also contains attenuated components at the line frequency and its harmonics, i.e., cos(ht), where h = 1, 2, 3, ... The magnitude response of the filter is given by
power signal. The average value of a sinusoidal signal is zero. Thus, the frequency generated by the ADE7752 is proportional to the average real power. Figure 27 shows the digital-tofrequency conversion for steady load conditions, i.e., constant voltage and current. As can be seen in the diagram, the frequency output CF varies over time, even under steady load conditions. This frequency variation is primarily due to the cos(2t) components in the instantaneous real power signal. The output frequency on CF can be up to 160 times higher than the frequency on F1 and F2. The higher output frequency is generated by accumulating the instantaneous real power signal over a much shorter time, while converting it to a frequency. This shorter accumulation period means less averaging of the cos(2t) component. As a consequence, some of this instantaneous power signal passes through the digital-to-frequency conversion. This will not be a problem in the application. Where CF is used for calibration purposes, the frequency should be averaged by the frequency counter. This will remove any ripple. If CF is being used to measure energy, e.g., in a microprocessor based application, the CF output should also be averaged to calculate power. Because the outputs F1 and F2 operate at a much lower frequency, much more averaging of the instantaneous real power signal is carried out. The result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output.
|H ( f )| =
1 f 1+ 8
2
(8)
Where the -3 dB cutoff frequency of the low-pass filter is 8 Hz. For a line frequency of 50 Hz, this would give an attenuation of the 2 (100 Hz) component of approximately -22 dB. The dominating harmonic will be twice the line frequency, i.e., cos(2t), due to the instantaneous power signal. Figure 27 shows the instantaneous real power signal at the output of the CF, which still contains a significant amount of instantaneous power information, i.e., cos (2t). This signal is then passed to the digital-to-frequency converter where it is integrated (accumulated) over time to produce an output frequency. This accumulation of the signal will suppress or average out any non-dc component in the instantaneous real
VA LPF MULTIPLIER IA
ABS
|X| DIGITAL-TOFREQUENCY
F1
FREQUENCY
VB LPF MULTIPLIER IB |X|
DIGITAL-TOFREQUENCY
F1 F2
TIME
CF CF
FREQUENCY
VC LPF MULTIPLIER IC LPF TO EXTRACT REAL POWER (DC TERM) |X| Vx I 2
TIME
cos(2t) ATTENUATED BY LPF
0
2
02676-A-027
FREQUENCY - RAD/S INSTANTANEOUS REAL POWER SIGNAL (FREQUENCY DOMAIN)
Figure 27. Real Power-to-Frequency Conversion
Rev. B | Page 18 of 24
ADE7752
MODE SELECTION OF THE SUM OF THE THREE ACTIVE ENERGIES
The ADE7752 can be configured to execute the arithmetic sum of the three active energies, Wh = WhA + WhB + WhC, or the sum of the absolute value of these energies, Wh = |WhA| + |WhB| + |WhC| The selection between the two modes can be made by setting the ABS pin. Logic high and logic low applied on the ABS pin correspond to the arithmetic sum and the sum of absolute values, respectively. When the sum of the absolute values is selected, the active energy from each phase is always counted positive in the total active energy. It is particularly useful in 3-phase 4-wire installation where the sign of the active power should always be the same. If the meter is misconnected to the power lines, i.e., CT connected in the wrong direction, the total active energy recorded without this solution can be reduced by two-thirds. The sum of the absolute values assures that the active energy recorded represents the actual active energy delivered. In this mode, the reverse power pin still detects when negative power is present on any of the three phase inputs.
POWER MEASUREMENT CONSIDERATIONS
Calculating and displaying power information will always have some associated ripple that will depend on the integration period used in the MCU to determine average power as well as the load. For example, at light loads, the output frequency may be 10 Hz. With an integration period of 2 seconds, only about 20 pulses will be counted. The possibility of missing one pulse always exists since the ADE7752 output frequency is running asynchronously to the MCU timer. This would result in a 1-in20 or 5% error in the power measurement.
Rev. B | Page 19 of 24
ADE7752 TRANSFER FUNCTION
FREQUENCY OUTPUTS F1 AND F2
The ADE7752 calculates the product of six voltage signals (on current channel and voltage channel) and then low-pass filters this product to extract real power information. This real power information is then converted to a frequency. The frequency information is output on F1 and F2 in the form of active high pulses. The pulse rate at these outputs is relatively low, e.g., 29.32 Hz maximum for ac signals with SCF = 1; S0 = S1 = 1. (See Table 6.) This means that the frequency at these outputs is generated from real power information accumulated over a relatively long period of time. The result is an output frequency that is proportional to the average real power. The averaging of the real power signal is implicit to the digital-to-frequency conversion. The output frequency or pulse rate is related to the input voltage signals by the following equation: Freq = 5.922 x (V AN x I A + V BN x I B + VCN x I C ) x F VREF
2 1-7
F1-7 = 0.60 Hz, SCF = S0 = S1 = 1 VAN = VBN = VCN = IA = IB = IC = 500 mV dc = 0.5 V(rms of dc = dc) VREF = 2.4 V (nominal reference value) Note that if the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%. Freq = 3 x 5.922 x 0.5 x 0.5 x 0.60 2.4 2 = 0.462 Hz
Example 2
In this example, with ac voltages of 500 mV peak applied to the voltage channels and current channels, the expected output frequency is calculated as follows:
F1-7 = 0.60 Hz , SCF = S0 = S1 = 1 V AN = V BN = VCN = IA = IB = IC 0. 5 = 500 mV peak AC = Vrms 2 VREF = 2.4 V (nominal reference value ) Note that if the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%. Freq = 3 x 5.922 x 0.5 x 0.5 x 0.596 2 x 2 x 2. 4 2 = 0.23 Hz
where: Freq = Output frequency on F1 and F2 (Hz) VAN, VBN, and VCN = Differential rms voltage signal on voltage channels (Volts) IA, IB, and IC = Differential rms voltage signal on current channels (Volts) VREF = The reference voltage (2.4 V 8%) (Volts) F1-7 = One of seven possible frequencies selected by using the logic inputs SCF, S0, and S1. See Table 5.
Table 5. F1-7 Frequency Selection1
SCF 0 1 0 1 0 1 0 1
1
S1 0 0 0 0 1 1 1 1
S0 0 0 1 1 0 0 1 1
F1-7 (Hz) 1.27 1.19 5.09 4.77 19.07 19.07 76.29 0.60
As can be seen from these two example calculations, the maximum output frequency for ac inputs is always half of that for dc input signals. The maximum frequency also depends on the number of phases connected to the ADE7752. In a 3-phase 3-wire Delta service, the maximum output frequency is different from the maximum output frequency in a 3-phase 4-wire Wye service. The reason is that there are only two phases connected to the analog inputs, but also that in a Delta service, the current channel input and voltage channel input of the same phase are not in phase in normal operation.
F1-7 is a fraction of the master clock and therefore will vary if the specified CLKIN frequency is altered.
Example 3
In this example, the ADE7752 is connected to a 3-phase 3-wire Delta service as shown in Figure 21. The total real energy calculation processed in the ADE7752 can be expressed as Total Real Power = (VA - VC) x IA + (VB - VC) x IB Where VA, VB, and VC represent the voltage on phase A, B, and C, respectively. IA and IB represent the current on phase A and B, respectively.
Example 1
Thus, if full-scale differential dc voltages of +500 mV are applied to VA, VB, VC, IA, IB, and IC, respectively (500 mV is the maximum differential voltage that can be connected to current and voltage channels), the expected output frequency is calculated as follows:
Rev. B | Page 20 of 24
ADE7752
As the voltage and current inputs respect Equations 5 and 6, the total real power (P) is
Freq = 2 x
P = (VA - VC )
(IAP - IAN ) + (VB - VC ) x (IBP - IBN )
5.922 x 0.5 x 0.5 x 0.60 3 x = 0.134 Hz 2 2 x 2 x 2.4 2
4 P = 2 x V A x cos( l t ) - 2 x VC x cos l t + 3 x 2 x I A x cos( l t ) 2 4 + 2 x V B x cos l t + - v 2 x VC x cos l t + 3 3 2 x 2 x I B x cos l t + 3 For simplification, we assume that A = B = C = 0 and VA = VB = VC = V. The preceding equation becomes:
2 2 P = 2 x V x I A x sin x sin l t + x cos( l t ) 3 3 (9) 2 + 2 x V x I B x sin x sin( l t + )x cos l t + 3 3 P then becomes: 2 2 P = VAN x I A x sin + sin 2 l t + 3 3 + VBN x I B x sin + sin 2 l t + 3 3 where VAN = V x sin(2/3) and VBN = V x sin(/3). As the LPF on each channel eliminates the 2l component of the equation, the real power measured by the ADE7752 is P = V AN x I A x 3 3 + V BN x I B x 2 2
Table 6 shows a complete listing of all maximum output frequencies when using all three channel inputs.
Table 6. Maximum Output Frequency on F1 and F2
SCF 0 1 0 1 0 1 0 1 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 Max Frequency for AC Inputs (Hz) 0.49 0.46 1.95 1.83 7.33 7.33 29.32 0.23 Max Frequency for DC Inputs (Hz) 0.98 0.91 3.91 3.67 14.66 14.66 58.65 0.46
FREQUENCY OUTPUT CF
The pulse output CF (calibration frequency) is intended for use during calibration. The output pulse rate on CF can be up to 160 times the pulse rate on F1 and F2. The lower the F1-7 frequency selected, the higher the CF scaling. Table 7 shows how the two frequencies are related, depending on the states of the logic inputs S0, S1, and SCF. Because of its relatively high pulse rate, the frequency at this logic output is proportional to the instantaneous real power. As is the case with F1 and F2, the frequency is derived from the output of the low-pass filter after multiplication. However, because the output frequency is high, this real power information is accumulated over a much shorter time. Thus, less averaging is carried out in the digital-tofrequency conversion. With much less averaging of the real power signal, the CF output is much more responsive to power fluctuations. See Figure 15.
Table 7. Maximum Output Frequency on CF
SCF 0 1 0 1 0 1 0 1 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 F1-7 (Hz) 1.27 1.19 5.09 4.77 19.07 19.07 76.29 0.60 CF Max for AC Signals (Hz) 160 x F1, F2 = 78.19 8 x F1, F2 = 3.66 160 x F1, F2 = 312.77 16 x F1, F2 = 29.32 16 x F1, F2 = 117.3 8 x F1, F2 = 58.65 8 x F1, F2 = 234.59 16 x F1, F2 = 3.67
(10)
If full-scale ac voltage of 500 mV peak is applied to the voltage channels and current channels, the expected output frequency is calculated as follows:
F1-7 = 0.60Hz , SCF = S0 = S1 = 1 V AN = V BN = IA = IB = IC = 500 mV peak ac = VCN = IC = 0 VREF = 2.4V nominal reference value Note that if the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%. 0.5 V rms 2
Rev. B | Page 21 of 24
ADE7752 SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION
As shown in Table 5, the user can select one of seven frequencies. This frequency selection determines the maximum frequency on F1 and F2. These outputs are intended to be used to drive the energy register (electromechanical or other). Since only seven different output frequencies can be selected, the available frequency selection has been optimized for a 3-phase 4-wire service with a meter constant of 100 imp/kWhr and a maximum current of between 10 A and 100 A. Table 8 shows the output frequency for several maximum currents (IMAX) with a line voltage of 220 V (phase neutral). In all cases, the meter constant is 100 imp/kWhr
Table 8. V. F1 and F2 Frequency at 100 imp/kWhr
IMAX (A) 10 25 40 60 80 100 F1 and F2 (Hz) 0.10 0.25 0.40 0.60 0.80 1.00
When selecting a suitable F1-7 frequency for a meter design, the frequency output at IMAX (maximum load) with a 100 imp/kWhr meter constant should be compared with Column 5 of Table 9 The frequency that is closest in Table 9 will determine the best choice of frequency (F1-7). For example, if a 3-phase 4-wire Wye meter with a 25 A maximum current is being designed, the output frequency on F1 and F2 with a 100 imp/kWhr meter constant is 0.25 Hz at 25 A and 220 V (from Table 8). Looking at Table 9, the closest frequency to 0.25 Hz in Column 5 is 0.24 Hz. Therefore, F1-7 = 1.27 Hz is selected for this design.
FREQUENCY OUTPUTS
Figure 2 shows a timing diagram for the various frequency outputs. The outputs F1 and F2 are the low frequency outputs that can be used to directly drive a stepper motor or electromechanical impulse counter. The F1 and F2 outputs provide two alternating high going pulses. The pulse width (t1) is set at 275 ms, and the time between the rising edges of F1 and F2 (t3) is approximately half the period of F1 (t2). If, however, the period of F1 and F2 falls below 550 ms (1.81 Hz), the pulse width of F1 and F2 is set to half of their period. The maximum output frequencies for F1 and F2 are shown in Table 6. The high frequency CF output is intended to be used for communications and calibration purposes. CF produces a 96 mswide active high pulse (t4) at a frequency proportional to active power. The CF output frequencies are given in Table 7. As in the case of F1 and F2, if the period of CF (t5) falls below 192 ms, the CF pulse width is set to half the period. For example, if the CF frequency is 20 Hz, the CF pulse width is 25 ms. One exception to this is when the mode is S0 = 1, SCF = S1 = 0. In this case, the CF pulse width is 66% of the period.
The F1-7 frequencies allow complete coverage of this range of output frequencies on F1 and F2. When designing an energy meter, the nominal design voltage on the voltage channels should be set to half scale to allow for calibration of the meter constant. The current channel should also be no more than half scale when the meter sees maximum load. This will allow overcurrent signals and signals with high crest factors to be accommodated. Table 9 shows the output frequency on F1 and F2 when all six analog inputs are half scale.
Table 9. F1 and F2 Frequency with Half-Scale AC Inputs
SCF 0 1 0 1 0 1 0 1 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 F1-7 1.27 1.19 5.09 4.77 19.07 19.07 76.29 0.60 Frequency on F1 and F2 (Half-Scale AC Inputs) 0.24 0.23 0.98 0.92 3.67 3.67 14.66 0.11
Rev. B | Page 22 of 24
ADE7752
NO LOAD THRESHOLD
The ADE7752 also includes no load threshold and start-up current features that eliminate any creep effects in the meter. The ADE7752 is designed to issue a minimum output frequency. Any load generating a frequency lower than this minimum frequency will not cause a pulse to be issued on F1, F2, or CF. The minimum output frequency is given as 0.005% of the full-scale output frequency for each of the F1-7 frequency selections or approximately 0.00204% of the F1-7 frequency (see Table 10). For example, for an energy meter with a 100 imp/kWhr meter constant using F1-7 (4.77 Hz), the minimum output frequency at F1 or F2 would be 9.15 x 10-5 Hz. This would be 1.46 x 10-6 Hz at CF (16 x F1 Hz). In this example, the no load threshold would be equivalent to 3.3 W of load or a start-up current of 13.75 mA at 240 V.
Table 10. CF, F1, and F2 Minimum Frequency at No Load Threshold
SCF 0 1 0 1 0 1 0 1 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 F1, F2 Min (mHz) 2.44 x 10-5 2.29 x 10-5 9.77 x 10-5 9.16 x 10-5 3.67 x 10-4 3.67 x 10-4 1.47 x 10-3 1.15 x 10-5 CF Min (mHz) 3.91 x 10-3 1.83 x 10-4 1.56 x 10-2 1.47 x 10-3 5.86 x 10-3 2.93 x 10-3 1.17 x 10-2 1.83 x 10-4
NEGATIVE POWER INFORMATION
The ADE7752 detects when the current and voltage channels of any of the three phase inputs have a phase difference greater than 90, i.e., A or B or C > 90. This mechanism can detect wrong connection of the meter or generation of active energy. The NEGP pin output will go active high when negative power is detected on any of the three phase inputs. If positive active energy is detected on all the three phases, NEGP pin output is low. The NEGP pin output changes state at the same time as a pulse is issued on CF. If several phases measure negative power, the NEGP pin output will stay high until all the phases measure positive power. If a phase has gone below the NO LOAD threshold, NEGP detection on this phase is disabled. NEGP detection on this phase resumes when the power returns out of NO LOAD condition. See the No Load Threshold section.
Rev. B | Page 23 of 24
ADE7752 OUTLINE DIMENSIONS
15.60 (0.6142) 15.20 (0.5984)
24 13
7.60 (0.2992) 7.40 (0.2913)
1 12
10.65 (0.4193) 10.00 (0.3937)
2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 1.27 (0.0500) BSC 0.10 0.51 (0.020) 0.31 (0.012) 8 SEATING 0.33 (0.0130) 0 PLANE 0.20 (0.0079)
0.75 (0.0295) x 45 0.25 (0.0098)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 28. 24-Lead Standard Small Outline Package [SOIC] Wide Body (RW-24) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADE7752AR ADE7752ARRL EVAL-ADE7752EB Package Description SOIC Package SOIC Package ADE7752 Evaluation Board Package Option RW-241 RW-24 on 13" Reels
1
RW = Small Outline Wide Body Package in Tubes
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C02676-0-9/03(B)
Rev. B | Page 24 of 24

▲Up To Search▲

Price & Availability of ADE7752

	To Download ADE7752 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .